Learning tool for converting boolean expression and logic circuit diagram
| dc.contributor.author | Khedika, S | |
| dc.contributor.author | Rathnathevi, R | |
| dc.contributor.author | Sagirtha(, S | |
| dc.contributor.author | Mathialakan, T | |
| dc.contributor.author | Kanaganathan, S | |
| dc.date.accessioned | 2015-09-04T03:18:31Z | |
| dc.date.available | 2015-09-04T03:18:31Z | |
| dc.date.issued | 2013-07-06 | |
| dc.description.abstract | An endeavor has made to develop an application software tool called “Logic Circuit Diagram Designer”. Logic Circuit Diagram Designer is a learning tool for Logical Circuit Designing and simplifying Boolean expression. This paper explains algorithm and methodology for transforming Boolean Expression into Logic Circuit diagram and transforming Logic circuit diagram into Boolean Expression. The Karnaugh-map technique is used to simplify the Boolean Expression. The versatile software Logic Circuit Diagram Designer has developed using C# language in Microsoft Visual Studio.Net 2008 | en_US |
| dc.identifier.citation | Proceedings of the Third International Symposium 2013, pp. 31-35 | |
| dc.identifier.issn | 9789556270426 | |
| dc.identifier.uri | http://ir.lib.seu.ac.lk/handle/123456789/378 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | South Eastern University of Sri lanka | en_US |
| dc.subject | Logical circuit | en_US |
| dc.subject | Boolean expression | en_US |
| dc.subject | Karnaugh-map | en_US |
| dc.title | Learning tool for converting boolean expression and logic circuit diagram | en_US |
| dc.type | Full paper | en_US |